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quad high-speed precision difet ? operational amplifier international airport industrial park ? mailing address: po box 11400 ? tucson, az 85734 ? street address: 6730 s. tucson blvd. ? tucson, az 85706 tel: (520) 746-1111 ? twx: 910-952-1111 ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? immediate product info: (800) 548-6132 difet ? , burr-brown corp. bifet ? , national semiconductor corp. features l wide bandwidth: 6.4mhz l high slew rate: 35v/ m s l low offset: 750 m v max l low bias current: 4pa max l low settling: 1.5 m s to 0.01% l standard quad pinout description the opa404 is a high performance monolithic difet ? (dielectrically-isolated fet) quad operational amplifier. it offers an unusual combination of very- low bias current together with wide bandwidth and fast slew rate. noise, bias current, voltage offset, drift, and speed are superior to bifet ? amplifiers. laser-trimming of thin-film resistors gives very low offset and driftthe best available in a quad fet op amp. the opa404's input cascode design allows high pre- cision input specifications and uncompromised high- speed performance. standard quad op amp pin configuration allows up- grading of existing designs to higher performance levels. the opa404 is unity-gain stable. opa404 applications l precision instrumentation l optoelectronics l sonar, ultrasound l professional audio equipment l medical equipment l detector arrays cascode +in ?n output opa404 simplified circuit (each amplifier) +v cc ? cc ? 1986 burr-brown corporation pds-677f printed in u.s.a. august 1995 sbos149
2 opa404 specifications electrical at v cc = 15vdc and t a = +25 c unless otherwise noted. opa404ag, kp, ku (1) opa404bg opa404sg parameter conditions min typ max min typ max min typ max units input noise voltage: f o = 10hz 32 * * nv/ ? hz f o = 100hz 19 * * nv/ ? hz f o = 1khz 15 * * nv/ ? hz f o = 10khz 12 * * nv/ ? hz f b = 10hz to 10khz 1.4 * * m vrms f b = 0.1hz to 10hz 0.95 * * m vp-p current: f b = 0.1hz to 10hz 12 * * fa, p-p f o = 0.1hz thru 20khz 0.6 * * fa/ ? hz offset voltage input offset voltage v cm = 0vdc 260 1mv * 750 * * m v kp, ku 750 2.5mv m v average drift t a = t min to t max 3* * m v/ c kp, ku 5 m v/ c supply rejection v cc = 12v to 18v 80 100 86 * * * db kp, ku 76 100 db channel separation 100hz, r l = 2k w 125 * * db bias current input bias current v cm = 0vdc 1 8* 4**pa kp, ku 1 12 pa offset current input offset current v cm = 0vdc 0.5 8 * 4 * * pa kp, ku 0.5 12 pa impedance differential 10 13 || 1 * * w || pf common-mode 10 14 || 3 * * w || pf votage range common-mode input range 10.5 +13, C11 * * * * v common-mode rejection v in = 10vdc 88 100 92 * * * db kp, ku 84 100 db open-loop gain, dc open-loop voltage gain r l 3 2k w 88 100 92 * * * db frequency response gain bandwidth gain = 100 4 6.4 5 * * * mhz full power response 20vp-p, r l = 2k w 570 * * khz slew rate v o = 10v, r l = 2k w 24 35 28 * * * v/ m s settling time: 0.1% gain = C1, r l = 2k w 0.6 * * m s 0.01% c l = 100 pf, 10v step 1.5 * * m s rated output voltage output r l = 2k w 11.5 +13.2, C13.8 * * * * v current output v o = 10vdc 5 10 * * * * ma output resistance 1mhz, open loop 80 * * w load capacitance stability gain = +1 1000 * * pf short circuit current 10 27 40 * * * * * * ma power supply rated voltage 15 * * vdc voltage range, derated performance 5 18 * * * * vdc current, quiescent i o = 0madc 9 10 * * * * ma temperature range specification ambient temperature C25 +85 * * C55 +125 c kp, ku 0 +70 c operating ambient temperature C55 +125 * * * * c kp, ku C25 +85 c storage ambient temperature C65 +150 * * * * c kp, ku C40 +125 c q junction-ambient 100 * * c/w kp, ku 120/100 c/w *specifications same as opa404ag. note: (1) opa404ku may be marked opa404u. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or omissions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems.
3 opa404 electrical (full temperature range specifications) at v cc = 15vdc and t a = t min to t max unless otherwise noted. opa404ag, kp, ku opa404bg opa404sg parameter conditions min typ max min typ max min typ max units temperature range specification range ambient temperature C25 +85 * * C55 +125 c kp, ku 0 +70 c input offset voltage input offset voltage v cm = 0vdc 450 2mv * 1.5mv 550 2.5mv m v kp ku 1 3.5 mv average drift 3* * m v/ c kp, ku 5 m v/ c supply rejection 75 96 80 * 70 93 db bias current input bias current v cm = 0vdc 32 200 * 100 500 5na pa offset current input offset current v cm = 0vdc 17 100 * 50 260 2.5na pa voltage range common-mode input range 10 12.7, C10.6 * * 10 +12.6, C10.5 v common-mode rejection v in = 10vdc 82 99 86 * 80 88 db kp, ku 80 99 db open-loop gain, dc open-loop voltage gain r l 3 2k w 82 94 86 * 80 88 db rated output voltage output r l = 2k w 11.5 12.9, C13.8 * * 11 +12.7, C13.8 v current output v o = 10vdc 5 9** * 8ma short circuit current v o = 0vdc 8 20 50* ***** ma power supply current, quiescent i o = 0madc 9.3 10.5 * * 9.4 11 ma * specification same as opa404ag. ordering information temperature model package range opa404kp 14-pin plastic dip 0 c to +70 c opa404ku (1) 16-pin plastic soic 0 c to +70 c opa404ag 14-pin ceramic dip C25 c to +85 c opa404bg 14-pin ceramic dip C25 c to +85 c opa404sg 14-pin ceramic dip C55 c to +125 c note: (1) opa404ku may be marked opa404u. package information package drawing model package number (1) opa404kp 14-pin plastic dip 010 opa404ku (2) 16-pin plastic soic 211 opa404ag 14-pin ceramic dip 169 opa404bg 14-pin ceramic dip 169 opa404sg 14-pin ceramic dip 169 note: (1) for detailed drawing and dimension table, please see end of data sheet, or appendix d of burr-brown ic data book. (2) opa404ku may be marked opa404u. pin configuration top view u (soic) package top view g or p (dip) package absolute maximum ratings supply ............................................................................................. 18vdc internal power dissipation (1) ......................................................... 1000mw differential input voltage (2) ............................................................. 36vdc input voltage range (2) ................................................................... 18vdc storage temperature range ... p, u = C40 c/+125 c, g = C65 c/+150 c operating temperature range .. p, u = C25 c/+85 c, g = C55 c/+125 c lead temperature (soldering, 10s) .................................................... 300 c soic (soldering, 3s) ..................................................................... +260 c output short-circuit duration (3) ................................................. continuous junction temperature ....................................................................... +175 c notes: (1) packages must be derated based on q jc = 30 c/w or q ja = 120 c/w. (2) for supply voltages less than 18vdc the absolute maximum input voltage is equal to: 18v > v in > Cv cc C 8v. see figure 2. (3) short circuit may be to power supply common only. rating applies to +25 c ambient. observe dissipation limit and t j . a b d c 1 2 3 4 5 6 7 out a ?n a + in a + v cc +in b ?in b out b 14 13 12 11 10 9 8 out d ?n d +in d ? cc +in c ?n c out c a b d c 1 2 3 4 5 6 7 8 out a ?n a + in a + v cc +in b ?in b out b nc 16 15 14 13 12 11 10 9 out d ?n d +in d ? cc +in c ?n c out c nc
4 opa404 dice information pad function 8 output c 9 Cinput c 10 +input c 11 Cv cc 12 +input d 13 Cinput d 14 output d pad function 1 output a 2 Cinput a 3 +input a 4+v cc 5 +input b 6 Cinput b 7 output b mechanical information mils (0.001") millimeters die size 108 x 108 5 2.74 x 2.74 0.13 die thickness 20 3 0.51 0.08 min. pad size 4 x 4 0.10 x 0.10 backing none substrate bias: Cv cc nc: no connection 1 2 3 4 nc 89 10 11 nc 12 nc 13 14 nc nc 5 6 7 nc opa404 die topography typical performance curves t a = +25 c, v cc = 15vdc unless otherwise noted. 1 10 100 1k 10k 100k 1m frequency (hz) 0.1 100 10 1 current noise (fa/ hz) input current noise spectral density 100 1k 10k 100k 1m 10m 100m source resistance ( ) 1 1k 100 10 voltage noise, e o (nv/ hz) total input voltage noise spectral density at 1khz vs source resistance w opa404 + resistor e o s r resistor noise only ?5 ?0 0 +25 +50 +100 +125 temperature (?) 90 110 105 95 cmr and psr (db) power supply rejection and common-mode rejection vs temperature 100 ?5 +75 psr cmr ?0 +25 ?5 0 +50 +75 +100 +125 ambient temperature (?) 0.1 1 10 100 1na 10na bias current (pa) bias and offset current vs temperature 0.1 1 10 100 1na 10na offset current (pa) bias current offset current
5 opa404 typical performance curves (cont) t a = +25 c, v cc = 15vdc unless otherwise noted. ?5 ?0 ? 0 +5 +10 +15 common-mode voltage (v) 0.01 10 1 0.1 bias current (pa) bias and offset current vs input common-mode voltage 0.01 10 1 0.1 offset current (pa) offset current bias current 11k 10 100 10k 100k 1m 10m frequency (hz) 0 20 40 60 80 100 120 140 common-mode rejection (db) common-mode rejection vs frequency 11k 10 100 10k 100k 1m 10m frequency (hz) 0 20 40 60 80 100 120 140 voltage gain (db) open-loop frequency response ?80 ?35 ?0 ?5 phase shift (degrees) a ol r l = 2k w c l = 100pf 11k 10 100 10k 100k 1m 10m frequency (hz) 0 20 40 60 80 100 120 140 power supply rejection (db) power supply rejection vs frequency + ?5 ?0 0 +5 +10 +15 common-mode voltage (v) 70 120 80 common-mode rejection (db) common-mode rejection vs input common-mode voltage 90 ? 100 110 ?5 ?0 0 +25 +50 +100 +125 ambient temperature (?) 2 10 8 4 gain bandwidth (mhz) gain bandwidth and slew rate vs temperature 6 ?5 +75 33 40 36 34 slew rate (v/?) 35 gbw slew rate
6 opa404 01020 supply voltage (? cc ) 5 8 6 gain-bandwidth and slew rate vs supply voltage 7 515 32 38 34 gain bandwidth (mhz) 36 gbw slew rate r l = 10k w a v = +1 slew rate (v/?) ?5 ?0 0 +25 +50 +100 +125 ambient temperature (?) 80 120 110 90 voltage gain (db) open-loop gain vs temperature 100 ?5 +75 small signal transient response time(?) 012 output voltage (mv) 0 C50 C100 100 C150 50 150 large signal transient response time(?) 01 234 5 output voltage (v) 10 0 C10 typical performance curves (cont) t a = +25 c, v cc = 15vdc unless otherwise noted. 10k 100k 10m frequency (hz) 0 30 20 10 maximum output voltage swing vs frequency 1m r l = 2k w output voltage (vp-p) ? ?0 ?k closed-loop gain (v/v) 0 5 1 settling time vs closed-loop gain ?00 settling time (?) 2 3 4 0.01% c l = 100pf r l = 2k w 0.1%
7 opa404 typical performance curves (cont) t a = +25 c, v cc = 15vdc unless otherwise noted. 10 100 100k frequency (hz) 150 140 130 120 110 0 channel separation vs frequency 10k channel separation (db) 1k r l = 2k w r l = 0.1 1 10 100 1k 10k 100k frequency (hz) 1 0.1 0.01 0.001 thd + n (% rms) total harmonic distortion vs frequency 6.5vrms 40.2k w 2k w 402 w a v = +101v/v a v = +101v/v a v = +1v/v test limit 01020 supply voltage (? cc ) 92 104 96 open-loop gain vs supply voltage 100 515 voltage gain 1 10 100 1k 10k 100k 1m frequency (hz) 1k 100 10 1 voltage noise (nv/ hz) input voltage noise spectral density ?5 ?0 0 +25 +50 +100 +125 ambient temperature (?) 11 10 9 8 7 supply current (ma) ?5 +75 supply current vs temperature
8 opa404 applications information offset voltage adjustment the opa404 offset voltage is laser-trimmed and will require no further trim for most applications. if desired, offset volt- age can be trimmed by summing (see figure 1). with this trim method there will be no degradation of input offset drift. guarding and shielding as in any situation where high impedances are involved, careful shielding is required to reduce hum pickup in input leads. if large feedback resistors are used, they should also be shielded along with the external input circuitry. leakage currents across printed circuit boards can easily exceed the bias current of the opa404. to avoid leakage, utmost care must be used in planning the board layout. a guard pattern should completely surround the high imped- ance input leads and should be connected to a low-impedance point which is at the signal input potential. (see figure 3). figure 2. input current vs input voltage with v cc pins grounded. ?5 ?0 ? 0 +5 +10 +15 input voltage (v) ? +2 +1 ? input current (ma) input current vs input voltage with ? cc pins grounded 0 maximum safe current maximum safe current i in v figure 3. connection of input guard. handling and testing measuring the unusually low bias current of the opa404 is difficult without specialized test equipment; most commer- cial benchtop testers cannot accurately measure the opa404 bias current. low-leakage test sockets and special test fixtures are recommended if incoming inspection of bias current is to be performed. to prevent surface leakage between pins, the dip package should not be handled by bare fingers. oils and salts from fingerprints or careless handling can create leakage currents that exceed the specified opa404 bias currents. if necessary, dip packages and pc board assemblies can be cleaned with freon tf ? , baked for 30 minutes at 85 c, rinsed with de-ionized water, and baked again for 30 min- utes at 85 c. surface contamination can be prevented by the application of a high-quality conformal coating to the cleaned pc board assembly. ?5v +15v ?mv offset trim 150k w 100k w in out 20 w 1/4 opa404 figure 1. offset voltage trim. input protection conventional monolithic fet operational amplifiers require external current-limiting resistors to protect their inputs against destructive currents that can flow when input fet gate-to- substrate isolation diodes are forward-biased. most bifet amplifiers can be destroyed by the loss of Cv cc . unlike bifet amplifiers, the difet opa404 requires input current limiting resistors only if its input voltage is greater than 8 volts more negative than Cv cc . a 10k w series resistor will limit the input current to a safe value with up to 15v input levels even if both supply voltages are lost. (see figure 2 and absolute maximum ratings). static damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. in precision operational amplifiers (both bipolar and fet types), this may cause a noticeable degradation of offset voltage and drift. static protection is recommended when handling any preci- sion ic operational amplifier. in out non-inverting in out buffer in out inverting for input guarding, guard top and bottom of board.
9 opa404 bias current change vs common-mode voltage the input bias currents of most popular bifet operational amplifiers are affected by common-mode voltage (figure 4). higher input fet gate-to-drain voltage causes leakage and ionization (bias) currents to increase. due to its cascode input stage, the extremely low bias current of the opa404 is not compromised by common-mode voltage. applications circuits figures 5 through 11 are circuit diagrams of various appli- cations for the opa404. in out zero 1m w 2 3 1 6 7 5 polypropylene 1? gain = ?00 v os < 10? drift ? 0.05?/? zero droop ? 1?/s referred to input 1/4 opa404 100k w 10k w 100k w 100 w operate 1/4 opa404 ?0 ? 0 +5 +10 ?0 ?0 0 10 20 30 40 50 60 70 80 input bias current (pa) lf155 op-15/16/17 ad547 lf156/157 ad547 opa404 lf156/157 t a = +25?; curves taken from mfg. published typical data common-mode voltage (vdc) ?5 +15 lf155 opa404 figure 4. input bias current vs common-mode voltage. figure 5. auto-zero amplifier. figure 6. low-droop positive peak detector. input output 6 7 5 2 3 1 10k w in914 1m w 2n4117 0.01? polstyrene droop ? 0.1mv/s ? 10pf 1/4 opa404 1/4 opa404 in914 (1) (1) (1) note: (1) reverse polarity for negative peak detection.
10 opa404 figure 7. voltage-controlled microamp current source. figure 9. fet instrumentation amplifier with shield driver. figure 8. sensitive photodiode amplifier. e 1 e 1 output = 1?/v i o 1 2 3 1m w r 6 5 3 2 ina105 differential input 1 i o = (e 1 ?e 2 ) /r load 1/4 opa404 +15v output 0.01? guard pin photodiode udt pin-040a 2 3 8 4 1 ?5v <1pf to prevent gain peaking 5 x 8 8 v/w 0.1? 0.01? 1/4 opa404 circuit must be well shielded. 1000m w 1000m w 12 13 3 1 2 6 7 5 10 9 8 14 1/4 opa404 1/4 opa404 1/4 opa404 1/4 opa404 input + guard 20k w 20k w guard r f 10k w r f 10k w 20k w 20k w a v = 101?/v i ? 1pa r ? 10 13 w bw ? 100khz differential voltage gain = 1+ (2r f /r g ) b in r g /2 100 w r g /2 100 w
11 opa404 figure 10. 8-pole 10hz low-pass filter. figure 11. wide-band amplifier. gain = +1v/v 48db/octave, 10hz lpf butterworth response 0.47? 57.6k w 9.53k w 2 3 1 a 0.47? 44.2k w 12.1k w 4 5 7 b 0.22? 61.9k w 18.7k w 9 10 8 c 0.033? 127k w 60.4k w 13 12 14 d 1? 1? 1? 1? out in 1k w 1k w 1k w 1k w a out b c d 4.02k w 4.02k w 4.02k w 4.02k w a v = +635 bw ? 650khz gain-bandwidth ? 410mhz in
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) opa404ag nrnd cdip sb jd 14 1 green (rohs & no sb/br) au n / a for pkg type opa404bg nrnd cdip sb jd 14 1 green (rohs & no sb/br) au n / a for pkg type opa404kp active pdip n 14 25 green (rohs & no sb/br) cu nipdau n / a for pkg type opa404kpg4 active pdip n 14 25 green (rohs & no sb/br) cu nipdau n / a for pkg type opa404ku active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr opa404ku/1k active soic dw 16 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr opa404ku/1ke4 active soic dw 16 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr opa404kug4 active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr opa404sg nrnd cdip sb jd 14 1 green (rohs & no sb/br) au n / a for pkg type (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 25-may-2009 addendum-page 1
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant opa404ku/1k soic dw 16 1000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 q1 package materials information www.ti.com 11-mar-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) opa404ku/1k soic dw 16 1000 346.0 346.0 33.0 package materials information www.ti.com 11-mar-2008 pack materials-page 2
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